MIPS ISA

Instruction Set Architecture

• Includes everything programers need to know to make the machine code work correctly
• Allows computer designers to talk about functions independently from the hardware that performs them
• One ISA (e.g. MIPS) can be implemented by many processors

Instruction Formats

• R-format (Register format: op $rd, $rs, $rt)
  • 1 destination register and 2 source registers
  • Bit allocation
    • 6 bit opcode opcode : Is 0 for all r-format instructions
    • 5 bit source register rs : First operand (i.e. register addressing)
    • 5 bit target register rt : Second operand
    • 5 bit destination register rd : Where to store result
    • 5 bit shift amount shamt : Amount to shift, 0 for other instructions
    • 6 bit function code funct : Specifies the instruction
  • For sll and srl , the operand register is rt
• I-format (Immediate format: op $rt, $rs, Immd or op $rt Immd($rs))
  • 1 destination register, 1 source register, 1 immediate value
  • Bit allocation
    • 6 bit opcode opcode : Specifices the instruction
    • 5 bit source register rs : Operand
    • 5 bit target register rt : Where to store result
    • 16 bit immediate value : Treated as signed integer except for bitwise operation (andi, ori etc.), in 2s complement (i.e. immediate addressing)
  • For load and store instructions e.g. lw, the immediate value refers to the offset (i.e. base addressing), rs contains the address and rt is the register to store/load from
  • For beq and bne , Immd specifies the target instruction address relative to the current PC (Program Counter) (i.e. PC-relative addressing)
    • The value is the number of words (= number of instructions to skip over) i.e. it is always multiplied by 4
    • The branch can go $\pm 2^{15}$ instructions from the PC
    • PC value is updated by PC = (PC + 4) + (Immd * 4) if branch taken, else PC = PC + 4
• J-format (Jump format op Immd)
  • 1 immediate value
  • Bit allocation
    • 6 bit opcode opcode : Specifies the intsruction
    • 26 bit immediate value : Target address (ie.e pseudo direct addressing)
  • Jumping will always be word aligned (multiple of 4, the rightmost 2 bits will be 0). So the least significant two bits are not included in the address (so we can represent a 28 bit memory address)
  • The remaining most significant 4 bits are taken from PC+4 i.e. the current most significant 4 bits
  • Maximum jump range will be the current 256MB block of memory
  • If need more range, use the jr jump register instruction

Concepts of ISA Design

• Complex Instruction Set Computer (single instruction for complex operation)
• Reduced Instruction Set Computer (keep instruction set small and simple)

Data Storage

Where to get data?

• Stack architecture
  • Operands are implicitly placed on top of the stack
• Accumulator architecture
  • One operand is implicitly in the accumulator (a special register)
• Memory-memory architecture
  • All operands are in memory
• General purpose register architecture
  • Only explicit operands (operands are all defined in the instruction)
  • Register-memory architecture (one operand in memory) (CISC uses a combination of this and register-register)
  • Register-register archicterue or load-store architecture (This is RISC/MIPS)

Memory and Addressing Mode

How to access data in memory?

• How does the processor talk to the memory?
  • Memory Address Register
    • Stores the memory address that we want to read/write from
    • Uni-directional (one way) bus to the memory. Memory can only read from this register
    • The bus is 32-bit for MIPS (k-bit for architecture with k-bit addresses)
  • Memory Data Register
    • Stores the data that needs to be written or the data that has been read from the memory
    • Bi-directional bus to the memory. Memory can read and write from this register
    • The bus is n-bit
  • Control lines between processor and memory
    • Decide whether the current operation is read or write, etc.
• Endianness (the ordering of bytes in a multiple-byte word stored in memory)
  • Big endian: the most significant byte is stored in the lowest memory address
  • Little endian: the least significant byte is stored in the lowest memory address
• Addressing Modes (how operands are specified in assembly)
  • Register: Operand is in a register
  • Immediate: Operand is specified in the instruction directly
  • Displacement: Operand is in memory with address calculated as Base + Offset

Operations in Instruction Set

Types of supported operations

Instruction Formats

Types of instructions. Instruction Fields: opcode & operands

Encoding the Instruction Set

How instructions are encoded into binary